1. Field of the Invention
The present invention relates to input/output circuits for integrated circuits which include voltage protection circuitry and more particularly to an up-shift circuit for the protection circuitry.
2. Description of Related Art
In integrated circuit technology, devices in different integrated circuit (xe2x80x9cICxe2x80x9d) packages are interconnected to one another at input/output (I/O) pads. I/O pads are associated with electrical circuits which perform a desired function and interface with other IC packages or electrical devices. An I/O pad may be associated with electrical circuits which generate output signals and apply the signals to the I/O pad that external devices sense and process accordingly. Alternatively, an I/O pad may be associated with electrical circuits which sense the logic state of signals applied to the I/O pad by external electrical circuits or IC packages. I/O pads are frequently xe2x80x9cbi-directionalxe2x80x9d in the sense that they may be used at different times for the sensing of input signals to the IC package or for the application of output signals from the IC package.
Electrical output signals are applied to an I/O pad by electrical circuits within the IC package associated with the I/O pad. Similarly, electrical signals are received as input signals from an I/O pad by associated electrical circuits within the IC package which xe2x80x9csensexe2x80x9d the signal level and operate accordingly.
It is common for such interconnected circuits to utilize standard voltage levels to represent logic states of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. Common standard voltage levels in the past have been 0 Volts (+/xe2x88x92 a threshold value) to represent zero logic state and 5 Volts (+/xe2x88x92 a threshold value) to represent the one logic state. As new IC manufacturing technologies evolve, the voltage levels used to represent a logic one state have been reduced to 3.3 Volts, 2.5 Volts, and further to 1.8 Volts. The lower voltage levels permit reduced thickness in transistor gate oxide materials to thereby reduce switching time of transistor gates and improve performance of the switching circuitry.
As gate oxide thickness is reduced in advanced low voltage CMOS technologies protecting the input/output circuit""s dielectrics from over-voltage conditions becomes necessary when interfacing to higher voltage buses. What is needed is an input circuit fabricated in a 1.8 Volt CMOS technology which is compatible with 2.5 and 3.3 Volt low voltage transistor-transistor logic (LVTTL) bus wherein protection is provided to prevent verstressing gate oxide in the input circuit where undershoot/overshoot peaks of xe2x88x921 Volt to LVTTL levels of 3.6 Volts+associated overshoot can occur on the input.
Further, it is important to discuss some of the device physics which play a role in hot electron (hot exe2x88x92) field effect transistor (FET) degradation. For p+ diffusions in Nwell, separated by a poly gate, holes are accelerated across the channel, thereby inducing current in a P-type FET (PFET) device. Even though holes are the dominant population, it has been shown that electrons damage the integrity of the Sixe2x80x94O2 interface under a PFET gate. As holes are accelerated to high speeds, electrons coming in contact with holes get deflected and become trapped in the oxide. It is this trapping of electrons in the oxide that is responsible for changing the voltage threshold and current characteristics of a PFET device. The trapping problem is exacerbated at high voltage and at short channel lengths, as a higher field allows electrons to reach ever higher velocities and shorter channels increase the likelihood that an electron will collide with a hole and become embedded in the oxide defining the top of the PFET channel. Higher fields are typically encountered during In-Situ BURN-IN of a circuit, or field operation of the circuit at the highest voltage rating for the technology. The net affect is the PFETs, when exposed to high Vgs and high Vds become leaky over time and compromise the ability of the protection circuitry to shield the driver from voltage swings from 0 volts to LVTTL levels arriving at the PAD.
The invention comprises an input/output circuit of an integrated circuit chip that includes a pad, a protection circuit connected to the pad, and an up-shift circuit connected to the pad and the protection circuit. The up-shift circuit provides a DC bias voltage to signals received by the pad to protect the protection circuit. With the invention, the protection circuit includes devices having a single oxide depth thickness.
The up-shift circuit shifts a first voltage received by the pad to a second voltage higher than the first voltage. The first voltage is approximately 0V (Ground Potential) and the second voltage is approximately 0.4V.
The inventive structure includes a driver circuit connected to the pad, a protection circuit connected to pad, an up-shift circuit connected to pad and protection circuit and a driver circuit connected to the pad and the protect circuitry, wherein the protection circuit eliminates the prospect of current paths being established into the voltage rails via CMOS (e.g. 2.5V nominal) and LVTTL (e.g. 3.3V nominal) signals arriving from off-chip. The up-shift circuit raises voltages arriving from off-chip from Ground Potential to some greater value, serving to protect and improve reliability of the devices responsible for insuring no current paths are established into the voltage supply rails. In this way, gate to source transistor voltages of devices are reduced below a limit. Further, drain to source transistor voltages are reduced below a limit. CMOS (e.g. 2.7V max.) and LVTTL (e.g 3.6V max.) signals arriving from off-chip travel unabated thru the novel circuit to the devices responsible for insuring no current paths are established into the voltage supply rails.
The invention can be used to increase end-of-life operation of a dual-voltage I/O circuit, having VDD (1.8 v nominal) and VDD250 (2.5 v nominal) operating in a very thin single-oxide depth technology. The driver level-shifts it""s data input from 1.8 v (nominal) to 2.5 v Jedec industry standard CMOS voltage levels in addition to receiving Jedec industry standard LVTTL levels (e.g., 3.3 V) and Jedec industry standard CMOS (2.5V) without (a) requiring a dual-oxide fabrication processing or without (b) enduring excessive oxide stress or diffusion stress during the life of the circuits. Therefore, with the invention, the reliability of the input/output circuit is greatly increased. Reliability improvement can be measured in several ways. First, consider FET behavior. Reduced diffusion (Vds) stress and less oxide stress (Vgs) translates into threshold voltage shift (Vt) and therefore less device current degradation through the life of the circuit. By reducing the stress seen by key transistors, the circuit does the following:
1) Increases the EOL (end-of-life) operation of the protect circuitry. Less stress translates into longer field operation.
2) Inclusion of xe2x80x9cup-liftxe2x80x9d circuit has no affect on the speed or block delays associated with the driver or receiver. Speed is not compromised whatsoever. The scope of said circuit is to provide stress relief to primary devices responsible for xe2x80x9cprotectingxe2x80x9d the driver from high off-chip voltages arriving via the PAD node.
3) The invention offers the user a minimal increase in circuit overhead for a given IO design. A total of six new transistors (3 PFETs +3 NFETs) are required to reduce stressing of the xe2x80x9cprotectxe2x80x9d devices described as prior art by Chan et al., U.S. Pat. No. 5,635,861 incorporated herein by reference. Hence, the invention offers minimal increase in circuit area for a given IO cell physical layout. In fact, it would require less area than an IO requiring thicker oxide to service. NFET and PFET transistors are connected at the PAD. In this case, the higher oxide voltage requires a longer NFET and PFET channel length. Since outputs FET""s are quite large, implementing thick-oxide versions is a spatially demanding proposition.